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Senior ASIC Design Engineer - Displays

NVIDIA

Engineering & Technology

IT & Telecoms GHS Confidential
2 months ago

Job Summary

We are now looking for a Display ASIC Design Engineer! NVIDIA is seeking a passionate ASIC Design Engineers to craft and implement display subsystem in the world’s leading SoC's and GPU's. This position offers the opportunity to have a real impact in a dynamic, technology-focused company impacting various product lines from traditional computers to consoles and cars. We have crafted an exceptional team of people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of displays to get the best visual experience.

  • Minimum Qualification: MBA / MSc
  • Experience Level: Senior level
  • Experience Length: 10 years

Job Description/Requirements

What You Will Be Doing:

  • As a core member of our team, you will be responsible for the implementation of display sub-system modules.
  • Develop micro-architecture, implement design and follow through with full verification and coverage closure. Develop designs in Verilog and High Level Synthesis (HLS).
  • Collaborate and coordinate with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks.
  • Support the bring-up of various features at a system level in various pre-silicon platforms like SOCV, Emulation, FPGA.
  • Support post-silicon validation activities for your designs.


What we need to see:

  • Bachelors Degree in Electrical Engineering, Computer Engineering or Computer Science (or equivalent experience).
  • At least 8 years of meaningful ASIC Design experience.
  • Experience in developing comprehensive micro-architecture documents for complicated design blocks.
  • Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic, Image/Pixel processing algorithms.
  • Good understanding of ASIC design flow including RTL design, CDC, logic synthesis, timing analysis and CDC.


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